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Chapter 22: Storage Library
22–21
In Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Arria GX, Arria II GX,
Cyclone III, Cyclone II, and Cyclone devices, the block implements a RAM-based shift
register that is useful for creating very large shift registers efficiently. The block
outputs occur at regularly spaced points along the shift register (that is, taps).
In Stratix devices, this block implements in the small memory.
Table 22–30 shows the Shift Taps block inputs and outputs.
Table 22–30. Shift Taps Block Inputs and Outputs
Signal
d
ena
t0–tn
sout
Direction
Input
Input
Output
Output
Description
Data input port.
Optional clock enable port.
Output ports for taps 0–n.
Optional shift out port.
Table 22–31 shows the Shift Taps block parameters.
Table 22–31. Shift Taps Block Parameters
Name
Number of Taps
Distance Between
Taps
Value
User Defined
(Parameterizable)
User Defined
(Parameterizable)
Description
Specifies the number of regularly spaced taps along the shift register.
Specifies the distance between the regularly spaced taps in clock cycles, which
translates to the number of RAM words that DSP Builder uses.
Use Shift Out Port On or Off
Turn on to create an output from the end of the shift register for cascading.
Use Enable port
Use Dedicated
Circuitry
Memory Block
Type
On or Off
On or Off
AUTO, M512, M4K,
M9K, MLAB, M144K
Turn on to use an additional clock enable control input.
Turn on to enable selection of the memory block type. This option is only valid
when the Distance Between Taps is greater than 2.
The RAM block type. Some memory types are not available for all device types.
Table 22–32 shows the Shift Taps block I/O formats.
Table 22–32. Shift Taps Block I/O Formats
(1)
I/O
Simulink
(2) , (3)
VHDL
Type
(4)
I
I1 [L1].[R1]
I2 [1]
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
Implicit
Explicit
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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